The present invention relates to a capacitor and a method for fabricating the capacitor, and a semiconductor device and a method for fabricating the semiconductor device, more specifically, a capacitor using a dielectric film of a high dielectric substance and a ferroelectric substance and a method for fabricating the capacitor, and a semiconductor device and a method for fabricating the semiconductor device.
Near an LSI (Large Scale Integrated circuit) or others mounted on a printed circuit board, decoupling capacitors are mounted for the prevention of erroneous operations due to source voltage changes and high-frequency noises.
The decoupling capacitor is formed on a support board different from the printed circuit board and are suitable mounted on the printed circuit board.
Recently, as higher speed and lower electric power consumption of LSIs, the characteristics of the decoupling capacitors are required to be improved. As LSIs, etc. are down-sized, the decoupling capacitors are also required to be down-sized.
Then, techniques of increasing the capacitance while satisfying the requirement of down-sizing the decoupling capacitors are proposed.
FIGS. 24A and 24B are a sectional view of the proposed decoupling capacitor.
As shown in FIGS. 24A and 24B, a lower electrode 118 of, e.g., Pt is formed on a base substrate 110.
A dielectric film 120 of BST ((Ba, Sr) TiO3), which is a dielectric substance, is formed on the lower electrode 118. The film thickness of the dielectric film 120 is, e.g., 200 nm.
An upper electrode 120 of, e.g., Pt is formed on the dielectric film 120.
The lower electrode 118, the dielectric film 120 and the upper electrode 128 constitute a capacitor 130.
A protection film 132 of polyimide is formed on the base substrate 110 with the capacitor 130 formed on.
An opening 134a and an opening 134b are formed in the protection film 132 respectively down to the upper electrode 128 and the lower electrode 118.
Vias 136a, 136 are formed respectively in the openings 134a, 134b. 
Solder bumps 138a, 138b are formed on the vias 136a, 136b. 
The upper electrode 128 of the capacitor 130 is electrically connected to the power source line of, e.g., a printed circuit board (not sown) via the via 134a, the solder bump 138a, etc.
The lower electrode 118 of the capacitor 130 is electrically connected to the earth wire of, e.g., the printed circuit board (not shown) via the via 134b, the solder bump 138b, etc.
Thus, the proposed decoupling capacitor is constituted.
The decoupling capacitor shown in FIGS. 24A and 24B uses a high dielectric substance as the material of the dielectric film 120, and besides, the dielectric film 120 is formed thin, whereby the capacitance can be increased while the requirement of down-sizing is satisfied.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. Hei 8-116032
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. 2000-509200